Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without a need for refreshing. SRAM cells may include different numbers of transistors, and are often accordingly referred to by the number of transistors, for example, six-transistor (6T) SRAM, eight-transistor (8T) SRAM, and the like. The transistors typically form a data latch for storing a bit. Additional transistors may be added to control the access to the transistors. SRAM cells are typically arranged as an array having rows and columns. Typically, each row of the SRAM cells is connected to a word-line, which determines whether the current SRAM cell is selected or not. Each column of the SRAM cells is connected to a bit-line, which is used for storing a bit into the SRAM cell or read from the SRAM cell.
With the scaling of integrated circuits, the operation voltages of integrated circuits are reduced, along with the operation voltages of memory circuits. Accordingly, read and write margins of the SRAM cells, which measure how reliably the bits of the SRAM cells can be read from and written into, respectively, are reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations. Conventionally, to improve the read and write margins, dynamic powers are provided, which means different power supply voltages VDD are provided for read and write operations. For example, the write margin can be improved by reducing the power supply voltage VDD during the write operations, while the read margin can be improved by increasing the power supply voltage VDD during the read operations. However, such a solution suffers drawbacks. The performance of the arrays is compromised due to the delay resulted from generating the dual power. In addition, complicated circuits have to be designed to provide dynamic power, which circuits occupy the chip space.
Accordingly, new SRAM arrays having improved read and write margins while at the same time overcoming the deficiency of the prior art are needed.